The present invention relates to a semiconductor integrated circuit and, more particularly, to a drive circuit used in a multi-channel semiconductor integrated circuit for driving a capacitive load such as a plasma display.
A conventional drive voltage supply circuit used in a multi-channel semiconductor integrated circuit will be described with reference to the drawings (see, e.g., Japanese Patent Application No. 2003-362063 (FIG. 4)).
FIG. 12 shows a structure of the conventional drive voltage supply circuit in a multi-channel semiconductor integrated circuit.
The drive voltage supply circuit shown in FIG. 12 comprises: a shift register 1 consisting of a plurality of latch circuits 1a; a gate circuit 2; a level shift circuit 4 connected to a power source terminal 9 and outputs a signal having the same polarity as an input thereto and a voltage obtained by shifting the voltage of the input; a high-side drive circuit 7 composed of a high-side transistor 3 controlled by the level shift circuit 4; low-side drive circuits 8 each connected between a common connection terminal 13 and a GND terminal 10 and composed of a low-side transistor 5 and a diode 6; and load capacitances 14 connected between the respective output terminals 11 of the low-side drive circuits 8 and a GND terminal. In FIG. 10, parasitic diodes 3a and 5a are shown individually for the high-side transistor 3 and the low-side transistors 5.
As shown in FIG. 12, it is assumed that, when a specified one of the plurality of low-side drive circuits 8 is mentioned, e.g., when the first one of the low-side drive circuits is mentioned, it will be hereinafter denoted as “low-side drive circuit 8(1)” and, when all or any of the low-side drive circuits are mentioned, they will be hereinafter denoted as the “low-side drive circuits 8”. The same notation shall apply to the low-side transistors 5, the diodes 6, the output terminals 11, the load capacitances 14, latch circuits 1a, and the parasitic diodes 3a and 5a which are the components of the low-side drive circuits 8.
Outputs Q which are sequentially outputted from the latch circuits 1a(1) to 1a(4n−3) each composing the shift register 1 are supplied to the gate circuit 2. An output signal from the gate circuit 2 is supplied to the level shift circuit 4. An output signal from the level shift circuit 4 controls the high-side transistor 3. On the other hand, the outputs Q which are sequentially outputted from the latch circuits 1a(1) to 1a(4n−3) control the low-side transistors 5(1) to 5(4n−3). By thus controlling the high-side transistor 3 and the low-side transistors 5, the states of the output terminals 11 are sequentially switched.
The conventional drive voltage supply circuit used in a multi-channel semiconductor integrated circuit has the structure in which the high-side transistor is shared by the plurality of low-side transistors. Accordingly, when the low-side transistor connected to a given one of the output terminals is ON, even though the low-side transistors connected to the other output terminals are OFF, the high-side transistor is turned OFF for the purpose of preventing a through current from flowing between the power source terminal and the GND terminal. In this manner, a path along which charge propagates is cut off by producing a high impedance state (hereinafter referred to as HIZ) so that the H level is maintained as a signal level at each of the output terminals. However, there has been a problem that, because of the HIZ state, an incoming disturbance causes an oscillation in the potential at any of the output terminals and the H level cannot be maintained any more.
A description will be given herein below to the problem of the oscillation in the potential at the output terminal caused by the disturbance in the HIZ state by using a case with a plasma display panel (hereinafter referred to as the PDP) as an example.
As shown in FIG. 13, the PDP comprises three electrodes which are a scan electrode 200, a sustain electrode 201, and a data electrode 202. Because each of the electrodes 200 to 202 is covered with a dielectric material, when viewed equivalently, it follows that capacitances 203, 204, and 205 are connected respectively between the electrodes 200 and 201, between the electrodes 201 and 202, and between the electrodes 200 and 202, as shown in FIG. 13. Accordingly, the output load of each of the drivers of the PDP becomes a capacitive load.
As shown in FIG. 13, a high-side transistor 208 and a low-side transistor 209 are connected between a power source terminal 206 and a GND terminal 207. When the low-side transistor 209 is OFF, the high-side transistor 208 is turned ON, whereby a H-level voltage is outputted to the scan electrode 200. Conversely, when the low-side transistor 209 is ON, the high-side transistor 208 is turned OFF, whereby a L-level voltage is outputted to the scan electrode 200. To each of the sustain electrode 201 and the data electrode 202 also, the H-level or L-level voltage is outputted with the same structure (a high side transistor 211 and a low-side transistor 212 each provided between a power source terminal 210 and a GND terminal 217 are connected to the sustain electrode 201, while a high-side transistor 215 and a low-side transistor 216 each provided between a power-source terminal 213 and a GND terminal 214 are connected to the data electrode 202) and under the same conditions as used for the scan electrode 200. In FIG. 13, the respective parasitic diodes (208a, 209a, 211a, 212a, 215a, and 216a) of the high-side transistors (208, 211, and 215) and the low-side transistors (209, 212, and 216) are shown.
Next, as an example of a disturbance (noise) resulting from the operation of an output signal from the data electrode 202, an oscillation caused by the disturbance in the output potential at the scan electrode 200 will be described herein below.
As shown in FIG. 14, when a data waveform applied to the data electrode 202 shifts from the L level to the H level at the time t1 and shifts from the H level to the L level at the time t2, noise enters the scan electrode 200 via the capacitance 205 to cause an undesirable oscillation in the potential at the scan electrode 200. In this case, when the high-side transistor 201 is ON, there is no problem because the oscillated potential at the scan electrode 200 returns to the same H level as the potential at the power source terminal 206 in a very short period of time. However, when each of the high-side transistor 208 and the low-side transistor 209 is OFF, the scan electrode 200 is in the HIZ state so that a path along which charge propagates is cut off. As a result, the noise from the data electrode 200 that has entered the scan electrode 200 via the capacitance 205 causes the oscillation in the potential at the scan electrode 200.
For example, as shown in FIG. 14, when the potential of the scan waveform applied to the scan electrode 200 oscillates to the H side at the time t1, it oscillates only to the level of a voltage (VDDH+VD) obtained by adding a forward voltage VD equivalent to the parasitic diode 208a to the power source voltage at the power source terminal 206. However, when the potential at the scan electrode 200 oscillates to the L side at the time t2, it undesirably oscillates to the level of a voltage (−VD) obtained by subtracting a forward voltage VD equivalent to the parasitic diode 209a from the voltage (VGND=0) at the GND terminal 207. As a result, the potential at the scan electrode 200 cannot retain the H level (power source voltage) and shifts to the L level.